Hard-Real-Time Inference for Physical AI on Heterogeneous Platforms
Experiments · method validationBuilding a hardware-grounded latency model that predicts latency for arbitrary matrix sizes and sequence lengths, and selects tilings and placements that keep end-to-end latency low under a latency and resource budget. Validating on SmolVLA, a vision-language-action model, running entirely on the AMD XDNA2 NPU. Hardware-aware GEMM and FlashAttention kernels, along with compiler fixes and support such as an A-stationary GEMM lowering, have landed upstream in AMD’s MLIR-AIR compiler. With hardware-aware tiling and 2D attention mapping, vision-stage latency drops 53.0% and end-to-end latency 43.0% over AMD’s original MLIR implementation, and 42.9% and 55.3%, respectively, over AMD’s Ryzen AI Software. End-to-end latency is also 13.5% lower than FastFlowLM. See public benchmarks here; ongoing work extends these gains further